1. Field of the Invention
The present invention relates to a data processing apparatus and method for performing hazard detection in respect of a series of access requests issued by processing circuitry for handling by one or more slave devices.
2. Description of the Prior Art
Efficient data communication between master devices and slave devices in data processing systems is a key factor in enhancing system performance. Data communication is typically mediated by communication buses and associated bus protocols. In its simplest form, the communication bus may take the form of a direct connection 30 between a master device 10 and a slave device 20 as shown schematically in FIG. 1A. However, more typically, as shown in FIG. 1B, the communication buses are implemented by an interconnect structure 70 used to couple a plurality of master devices 50, 60 with a plurality of slave devices 75, 80, 85. Each master device can issue access requests for handling by an addressed slave device. The handling of each access request involves an address transfer from a master device to a slave device, and one or more data transfers between that master device and the slave device. For a write access request these data transfers will pass from the master device to the slave device (in some implementations there will additionally be a write response transfer from the slave device to the master device), whilst for a read access request these data transfers will pass from the slave device to the master device.
The interconnect circuitry 70 will provide a plurality of connection paths for coupling the various master devices and slave devices. The way in which the various transfers are routed via those connection paths will be dependent on the bus protocol employed within the interconnect circuitry. One known type of bus protocol is the non-split transaction protocol, such as is employed within a data processing apparatus having an AHB bus designed in accordance with the AHB bus protocol developed by ARM Limited, Cambridge, United Kingdom.
As interconnect circuits increase in complexity, due to the need to support the interconnection of a large number of master and slave devices, then another type of bus protocol has been developed known as a split transaction protocol. In accordance with such a split transaction protocol, the plurality of connection paths within the interconnect circuit provide at least one address channel for carrying address transfers and at least one data channel for carrying data transfers. An example of such a split transaction protocol is the AXI (Advanced extensible Interface) protocol developed by ARM Limited, Cambridge, United Kingdom. The AXI protocol provides a number of channels over which information and data can be transferred, these channels comprising a read address channel for carrying address transfers for read access requests, a write address channel for carrying address transfers for write access requests, a write data channel for carrying data transfers for write access requests, a read data channel for carrying data transfers for read access requests, and a write response channel for returning transaction status information to the master device upon completion of a write access request. Use of such a split transaction protocol can increase the performance of a system compared with a similar system using a non-split transaction protocol.
It is known to issue access requests, whether write or read access requests, with identifier (ID) values associated therewith to identify the source of the access request. Any of the transfers taking place during processing of an access request are then also tagged with the associated ID value, to enable the various transfers involved in processing a particular access request to be tracked. Each master device may have a plurality of possible ID values that can be associated with access requests that it issues, thereby, for example, allowing transactions generated by different applications running on the same master to be distinguished from each other.
Irrespective of how the communication buses are constructed to allow communication between master and slave devices, one technique that is often adopted to seek to improve the performance of the data processing apparatus is to allow re-ordering of the transfers associated with various access requests, for example to seek to make more efficient use of the communication buses, to allow slave devices to operate more efficiently, etc. However, when allowing such re-ordering to take place, there is a potential for one or more hazard conditions to occur. For example, one hazard condition is a read after write (RAW) hazard condition which can occur when a master device wishes to issue a read access request to an address that is the subject of an already issued but still pending write access request. In such situations, the read access request should not be allowed to be processed until the write access request has completed since otherwise there is the possibility of the read occurring before the write.
Accordingly, it is known to provide hazard detection mechanisms within data processing systems to seek to detect the occurrence of possible hazard conditions, and to stall certain access requests when necessary to avoid those hazard conditions arising. For example, considering the earlier discussed AXI interconnect arrangement, master devices connected to an AXI interconnect are responsible for checking for RAW hazards for any write access requests that have been sent on the write address channel, and for which a write response has not yet been received. This requires the implementation of a mechanism for a master device to keep track of all pending write access requests.
However, the number of write access requests that may be pending at any one time will vary depending on how fast the master device can generate new write access requests, and also on how long any particular slave device takes to process write access requests and to send the write response. The latter is not easy to predict for a general purpose processor, as it may be connected to many different types of slave devices. Additionally, the amount of time that a slave device takes to return the write response may vary dynamically depending on, for example, how busy that slave device is. Therefore, determining how many write access requests the master device must be capable of hazard checking is difficult.
Previously, some master devices (for example the Cortex-R4 and Cortex-A9 processors developed by ARM Limited, Cambridge, United Kingdom) have implemented a fixed number of buffers for storing the addresses of at least certain types of write access requests that are pending. However, a problem that can arise is that if too few buffers are implemented then the performance of the master device can become restricted, since when all of the buffers of that master device are full, the master device must stall, and cannot send any further write access requests until space becomes available in one of the buffers. However, if enough buffers are implemented to cope with the worst case, then this has a high cost in terms of area and power due to the size and power consumption of the buffer circuitry.
An alternative approach, as for example is taken for non-cacheable write access requests in ARM's Cortex-A9 processor, is to use a counter to count the number of outstanding non-cacheable write access requests. This has the advantage that a large number of outstanding non-cacheable write access requests can be supported with very little area or power cost (due to the small size and low power consumption of the counter mechanism). However, since the counters cannot keep any record of the actual addresses involved in those pending write access requests, then when seeking to perform RAW hazard detection for any read access requests to be issued, it is not possible to do an address comparison with a pending write access request, and so it must pessimistically be assumed that the read address would match with the write address of a pending write access request, and accordingly the read access request must stall until all relevant outstanding write access requests complete.
Accordingly, it would be desirable to provide an improved technique for detecting one or more hazard conditions within such data processing systems.